The present invention relates to a programmable impedance circuit which carries out a impedance matching between a signal transmission line and an output buffer for the transmission of signals between semiconductor integrated circuits, and more specifically to a programmable impedance circuit capable of reducing the variance in the impedance value particularly in the case where the output voltage of the output buffer is in a transient state.
As the speed of the operation of semiconductor integral circuits is drastically increased recently, it becomes necessary to increase the speed of signal transmission carried out between semiconductor integrated circuits. One of the important factors for achieving a high speed signal transmission, is to carry out an impedance matching for matching impedance values of transmission lines and output buffers.
When the impedance value of a transmission line is set to Z0 and the impedance value of an output buffer is set to Zs, a reflection having a reflectance of .rho.=(Zs-Z0)/(Zs+Z0) occurs at a terminal of the transmission line if no termination is carried out.
In order to shorten the rise time or fall time of a transmission line, it is necessary to decrease the impedance value Zs of the output buffer. However, as is clear from the equation of the reflectance, when the Zs value is decreased extremely, data of opposite phase is reflected, and a ringing, in which the potential of a transmission line is vibrated, occurs.
FIG. 1 shows a normal waveform having no ringing, whereas FIG. 2 shows a waveform which contains a ringing. If a strong ringing occurs, it is no longer possible to carry out a normal data transmission. In order to transmit a signal at the maximum speed without causing a ringing, it is necessary to make the impedance value of the transmission line and the impedance value of the output buffer match with each other.
However, the impedance value of the transmission line varies depending upon the material of the printed board on which semiconductor integrated circuits are mounted. Therefore, it is difficult to make the impedance value of the output buffer of a semiconductor integrated circuit, and the impedance value of the transmission line to match with each other at all times.
Further, even if these impedance values are matched, the impedance value of the output buffer of the semiconductor integrated circuit is changed depending upon the conditions for operating a semiconductor integrated circuit (such as the temperature of the atmosphere and power voltage), in the case where the output buffer is made of MOS transistors only. As a result, an impedance matching cannot be achieved.
In order to solve the above-described drawback, a programmable impedance circuit capable of varying the impedance value of the output buffer programmably has been proposed. In the programmable impedance circuit of this type, the impedance value of a dummy resistance provided outside is monitored periodically, and the type and number of MOS transistors to be turned on, of those constituting the output buffer, are changed, so that the impedance value of the output buffer is set to an impedance value R (for example, R=r.times.1/5) which is proportional to the impedance value r of the dummy resistance. With this structure, it becomes possible to variably control the impedance value of the output buffer by setting the resistance value of the external dummy resistance.
FIG. 3 is a diagram showing an example of an output buffer of a conventional programmable impedance circuit.
The output buffer includes MOS transistors Q1 to Q6, NAND gates G1 to G4 and inverters INV1 to INV4, and complimentary input data up and down signals and binary section signals S1 and S2 are input from outside to the output buffer.
With the impedance value of the output buffer, selected by the binary selection signals S1 and S2, data having the same logic level as that of one of input data up signal of the complimentary input data is output. The input data up signal can be regarded as data for the "out" of the output buffer to output a logic level "1".
The circuit shown in FIG. 3 is divided into three buffer sections B1, B2 and B3. Of these sections, 2-bit binary section signals S1 and S2 are input respectively to the two buffer sections B2 and B3. The buffer section B1 is activated (turned on) at all times.
As the logic level of the binary section signals S1 and S2 is switched, any of the four types of the output impedance values for the output buffer is selected.
Further, by means of the buffer section B1 to which the binary selection signals S1 and S2 are not input, the maximum output impedance value is set.
The output buffer 4 in the conventional programmable impedance circuit shown in FIG. 3 is able to variably control the output impedance value by the logic level of the binary selection signals S1 and S2; however the programmable impedance circuit entails the following drawbacks which are caused by the characteristics of the output buffer.
That is, the output impedance value of the output buffer is adjusted to a value corresponding to the resistance value of the dummy resistance provided outside under a bias condition, and therefore it is not always possible to obtain a predetermined impedance value when the output voltage is in a transient state. For example, in the case where a circuit of the output buffer shown in FIG. 3 is formed of NMOS transistors, the characteristics of output-voltage to output-current will be as can be seen in FIG. 4 when the output voltage varies from a high level to a low level. The solid line in the figure represents an actually measured curve of output-voltage to output-current characteristics, and the dotted line represents an ideal straight line to be obtained in the case where the impedance value is assumed not to change.
As is clear from this figure, as the output voltage becomes higher, the deviation from the ideal straight line becomes more prominent, and thus the impedance value varies.
Further, FIG. 5 illustrates the relationship between an output voltage and an output current in the case where the signal voltage varies from a low level to a high level. This figure indicates that as the voltage level for specifying the selected impedance of the output buffer to match the impedance value of the transmission line and the impedance value of the output buffer, deviates from the dotted line which represents the ideal straight line to be obtained in the case where the impedance is assumed not to change, the impedance value of the output buffer varies more.
As described above, it is known that a ringing may occur in a transient state where the output voltage is varying, due to reflection.
It should be noted that the conventionally known programmable impedance circuit is discussed in Horald Piro et al., "A 300 MHz, 3.3V 1 Mb SRAM Fabricated in a 0.5 .mu.m CMOS Process" ISSCC Digest of Technical Papers, pp 148-149, 1996.